/**********************************************************************
	File: mask.v 
	
	Copyright (C) 2013  Alireza Monemi

    This program is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.
	
	
	Purpose:
	one niose microprocessor + nic and ram
**********************************************************************/


`include "define.v"
module cpu_core #(
	parameter VC_NUM_PER_PORT 		=	2,
	parameter PYLD_WIDTH 			=	32,
	parameter BUFFER_NUM_PER_VC	=	16,
	parameter FLIT_TYPE_WIDTH		=	2,
	parameter PORT_NUM				=	5,
	parameter X_NODE_NUM				=	4,
	parameter Y_NODE_NUM				=	3,
	parameter SW_X_ADDR				=	2,
	parameter SW_Y_ADDR				=	1,
	parameter NIC_CONNECT_PORT		=	0, // 0:Local  1:East, 2:North, 3:West, 4:South 
	parameter NIOS_RAM_WIDTH		=	13,
	parameter FIFO_FULL_WIDTH		=	VC_NUM_PER_PORT*2,
	parameter VC_ID_WIDTH			=	VC_NUM_PER_PORT,
	parameter FLIT_WIDTH				=	PYLD_WIDTH+FLIT_TYPE_WIDTH+VC_ID_WIDTH,
	parameter M_ADDR_SIZE			=	NIOS_RAM_WIDTH+2,
	parameter S_ADDR_SIZE			=	2,
	parameter CORE_NUMBER			=	`CORE_NUM(SW_X_ADDR,SW_Y_ADDR)
	
	)
	(
	
	input 											reset,
	input												nios_reset,   	
	input												clk,
	output											led,
// synthesis translate_off
	
	//avalon slave interface signals
	input												s_chipselect,
	input												s_write,
	input												s_read,
	input 	[S_ADDR_SIZE-1				:0]	s_address,
	input 	[31							:0]	s_writedata, 
	output	[31							:0] 	s_readdata,
	output											s_waitrequest,
	
	// simulatore 
	input   [ 31							: 0]	ram_data,
	input   [M_ADDR_SIZE-1				: 0]	ram_addr,
	input												ram_we,

// synthesis translate_on
	
	// NOC interfaces
	output	[FLIT_WIDTH-1				:0] 	flit_out,     
	output 		    			   				flit_out_wr,   
	//input 	[FIFO_FULL_WIDTH-1		:0]	flit_out_vc_full,
	input 	[VC_NUM_PER_PORT-1		:0]	credit_in,
	
	input		[FLIT_WIDTH-1				:0] 	flit_in,     // Data in
	input 	    			   					flit_in_wr,   // Write enable
	output 	[VC_NUM_PER_PORT-1		:0]	credit_out

	
	
	
); 
 




	
	//avalon master interface signals
	wire												m_chipselect;
	wire												m_write;
	wire												m_read;
	wire	 	[M_ADDR_SIZE-1				:0]	m_address;
	wire	 	[31							:0] 	m_writedata; 
	wire	 	[31							:0] 	m_readdata;
	wire												m_waitrequest;

`ifdef MODEL_TECH
	//code for modelsim 
	
	niosii_ram #(
			.DATA_WIDTH			(32),
			.ADDR_WIDTH			(NIOS_RAM_WIDTH+2),
			.CORE_NUMBER		(CORE_NUMBER)
	)
	the_ram
	(
		.address					(m_address) ,	
		.byteenable				() ,	
		.chipselect				(m_chipselect) ,	
		.clk						(clk) ,	
		.clken					() ,	
		.reset					(reset) ,	
		.write					(m_write) ,
		.writedata				(m_writedata),	
		.readdata				(m_readdata),
	
		.ram_data				(ram_data),
		.ram_addr				(ram_addr),
		.ram_we					(ram_we)
	);

`else 
 
  // code for synthesis

  //avalon slave interface signals
	wire												s_chipselect;
	wire												s_write;
	wire												s_read;
	wire 	[S_ADDR_SIZE-1					:0]	s_address;
	wire 	[31								:0]	s_writedata; 
	wire 	[31								:0] 	s_readdata;
	wire 												s_waitrequest;
  
  niosii_system	cpu (
		.clk_clk					(clk),           	//       	.clk.clk
		.reset_reset_n			(!reset),     		//     		.reset.reset_n
		.nios_rst_reset		(nios_reset),   	// 			.niose_reset
		.nic_m_write			(m_write),       	//     		.write
		.nic_m_read        	(m_read),			//          .read
		.nic_m_address     	(m_address),		//          .address
		.nic_m_writedata   	(m_writedata),		//          .writedata
		.nic_m_readdata    	(m_readdata),		//          .readdata
		.nic_m_waitrequest	(m_waitrequest), 	//          .waitrequest
		.nic_m_chipselect 	(m_chipselect), 	//          .chipselect
		
		.nic_s_chipselect		(s_chipselect),	// 			.chipselect
		.nic_s_write			(s_write),      	//          .write
		.nic_s_read        	(s_read),			//          .read
		.nic_s_address     	(s_address),		//          .address
		.nic_s_writedata   	(s_writedata),		//          .writedata
		.nic_s_readdata    	(s_readdata),		//          .readdata
		.nic_s_waitrequest  	(s_waitrequest),	//          .waitrequest
		.led_export 			(led)
		);
		
		
  
 `endif


 nic #(
	.VC_NUM_PER_PORT		(VC_NUM_PER_PORT),
	.PYLD_WIDTH 			(PYLD_WIDTH),
	.BUFFER_NUM_PER_VC	(BUFFER_NUM_PER_VC),
	.FLIT_TYPE_WIDTH		(FLIT_TYPE_WIDTH),
	.PORT_NUM				(PORT_NUM),
	.X_NODE_NUM				(X_NODE_NUM),
	.Y_NODE_NUM				(Y_NODE_NUM),
	.SW_X_ADDR				(SW_X_ADDR),
	.SW_Y_ADDR				(SW_Y_ADDR),
	.NIC_CONNECT_PORT		(NIC_CONNECT_PORT),
	.NIOS_RAM_WIDTH		(NIOS_RAM_WIDTH),
	.S_ADDR_SIZE			(S_ADDR_SIZE)
	)
	the_nic
	(
	
	.reset					(reset),
	.clk						(clk),
		
	// NOC interfaces
	.flit_out				(flit_out),     
	.flit_out_wr			(flit_out_wr), 
	.credit_in				(credit_in) ,	
	//.flit_out_vc_full		(flit_out_vc_full),
	.flit_in					(flit_in),     
	.flit_in_wr				(flit_in_wr) ,	
	.credit_out				(credit_out) ,	
	
	//avalon slave interface signals
	.s_chipselect			(s_chipselect) ,	
	.s_write					(s_write) ,	
	.s_read					(s_read) ,	
	.s_address				(s_address) ,	
	.s_writedata			(s_writedata) ,	
	.s_readdata				(s_readdata) ,	
	.s_waitrequest			(s_waitrequest) ,
	
	//avalon master interface signals
	
	.m_chipselect			(m_chipselect) ,	
	.m_write					(m_write) ,	
	.m_read					(m_read) ,	
	.m_address				(m_address) ,	
	.m_writedata			(m_writedata) ,	
	.m_readdata				(m_readdata) ,	
	.m_waitrequest			(m_waitrequest) 	

); 
 
 

 
 
 



endmodule
